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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. ad604 dual, ultralow noise variable gain amplifier features ultralow input noise at maximum gain: 0.80 nv/ hz , 3.0 pa/ hz 2 independent linear-in-db channels absolute gain range per channel programmable: 0 db to 48 db (preamp gain = 14 db), through 6 db to 54 db (preamp gain = 20 db) 1.0 db gain accuracy bandwidth: 40 mhz (? db) 300 k input resistance variable gain scaling: 20 db/v through 40 db/v stable gain with temperature and supply variations single-ended unipolar gain control power shutdown at lower end of gain control can drive adcs directly applications ultrasound and sonar time-gain control high performance agc systems signal measurement product description the ad604 is an ultralow noise, very accurate, dual-channel, linear-in-db variable gain amplifier (vga) optimized for time based variable gain control in ultrasound applications; however, it will support any application requiring low noise, wide band- width, variable gain control. each channel of the ad604 provides a 300 k w input resistance and unipolar gain control for ease of use. user determined gain ranges, gain scaling (db/v), and dc level shifting of output further optimize application perfor mance. each channel of the ad604 utilizes a high performance pre- amplifier that provides an input referred noise voltage of 0.8 nv/ hz . the very accurate linear-in-db response of the ad604 is achieved with the differential input exponential ampli fier (dsx-amp) architecture. each of the dsx-amps comprise a variable attenuator of 0 db to 48.36 db followed by a high speed fixed gain amplifier. the attenuator is based on a 7-stage r-1.5r ladder network. the attenuation between tap points is 6.908 db and 48.36 db for the ladder network. each independent channel of the ad604 provides a 48 db gain range that can be optimized for the application by programming the preamplifier with a single external resistor in the preamp feedback path. the linear-in-db gain response of the ad604 can be described by the equation g gain scaling / vgn preamp gain db db v v db db () = () () () + () () ? 19 functional block diagram out vocm pao pai differential attenuator + dsx ?dsx vgn vref r-1.5r ladder network 0 to ?48.4db programmable ultralow noise preamplifier g = 14db?20db precision passive input attenuator fixed gain amplifier 34.4db afa gain control and scaling preamplifier gains between 5 and 10 (14 db and 20 db) provide overall gain ranges per channel of 0 db through 48 db and 6 db through 54 db. the two channels of the ad 604 can be cascaded to provide greater levels of gain range by bypass ing the second channel?s preamplifier. however, in multiple channel systems, cascading the ad604 with other devices in the ad60x vga family that do not include a pream plifier may p rovide a more efficient solution. the ad604 provides access to the output of the preamplifier, allowing for external filtering between the preamplifier and the differential attenuator stage. the gain control interface of the ad604 provides an input resistance of approximately 2 m w and scale factors from 20 db/v to 30 db/v for a vref input voltage of 2.5 v to 1.67 v, respec- tively. note that scale factors up to 40 db/v are achievable with reduced accuracy for scales above 30 db/v. the gain scales linear-in-db with control voltages of 0.4 v to 2.4 v with the 20 db/v scale. below and above this gain control range, the gain begins to deviate from the ideal linear-in-db control law. the gain control region below 0.1 v is not used for gain control. in fact when the gain control voltage is <50 mv, the amplifier chan nel is powered down to 1.9 ma. the ad604 is available in a 24-lead ssop, soic, and pdip package and is guaranteed for operation over the ?40 c to +85 c temperature range.
rev. a ? ad604?pecifications parameter conditions min typ max unit input characteristics preamplifier input resistance 300 k w input capacitance 8.5 pf input bias current ?27 m a peak input voltage preamp gain = 14 db 400 mv preamp gain = 20 db 200 mv input voltage noise vgn = 2.9 v, r s = 0 w preamp gain = 14 db 0.8 nv/ hz preamp gain = 20 db 0.73 nv/ hz input current noise independent of gain 3.0 pa/ hz noise figure r s = 50 w , f = 10 mhz, vgn = 2.9 v 2.3 db r s = 200 w , f =10 mhz, vgn = 2.9 v 1.1 db dsx input resistance 175 w input capacitance 3.0 pf peak input voltage 2.5 2v input voltage noise vgn = 2.9 v 1.8 nv/ hz input current noise vgn = 2.9 v 2.7 pa/ hz noise figure r s = 50 w , f = 10 mhz, vgn = 2.9 v 8.4 db r s = 200 w , f =10 mhz, vgn = 2.9 v 12 db common-mode rejection ratio f = 1 mhz, vgn = 2.65 v ?20 db output characteristics ?3 db bandwidth constant with gain 40 mhz slew rate vgn = 1.5 v, output = 1 v step 170 v/ m s output signal range r l 500 w 2.5 1.5 v output impedance f = 10 mhz 2 w output short-circuit current 40 ma harmonic distortion vgn = 1 v, v out = 1 v p-p hd2 f = 1 mhz ?54 dbc hd3 f = 1 mhz ?67 dbc hd2 f = 10 mhz ?43 dbc hd3 f = 10 mhz ?48 dbc two-tone intermodulation vgn = 2.9 v, v out = 1 v p-p distortion (imd) f = 1 mhz ?74 dbc f = 10 mhz ?71 dbc third-order intercept f = 10 mhz, vgn = 2.65 v, ?12.5 dbm v out = 1 v p-p, input referred 1 db compression point f = 1 mhz, vgn = 2.9 v, output referred 15 dbm channel-to-channel crosstalk v out = 1 v p-p, f = 1 mhz ch no. 1: vgn = 2.65 v, inputs shorted ?30 db ch no. 2: vgn = 1.5 v (mid gain) db group delay variation 1 mhz < f < 10 mhz, full gain range 2ns vocm input resistance 45 k w accuracy absolute gain error 0 db to 3 db 0.25 v < vgn < 0.400 v ?1.2 +0.75 +3 db 3 db to 43 db 0.400 v < vgn < 2.400 v ?1.0 0.3 +1.0 db 43 db to 48 db 2.400 v < vgn < 2.65 v ?3.5 ?1.25 +1.2 db gain scaling error 0.400 v < vgn < 2.400 v 0.25 db/v output offset voltage vref = 2.500 v, vocm = 2.500 v ?50 30 +50 mv output offset variation vref = 2.500 v, vocm = 2.500 v 30 50 mv each amplifier channel at t a = 25 c, v s = 5 v, r s = 50 , r l = 500 , c l = 5 pf, v ref = 2.50 v (scaling = 20 db/v), 0 db to 48 db gain range (preamplifier gain = 14 db), vocm = 2.5 v, c1 and c2 = 0.1 f (see figure 35), unless otherwise noted.
rev. a ad604 ? specifications parameter conditions min typ max unit gain control interface gain scaling factor vref = 2.5 v, 0.4 v < vgn < 2.4 v 19 20 21 db/v vref = 1.67 v 30 db/v gain range preamp gain = 14 db 0 to 48 db preamp gain = 20 db 6 to 54 db input voltage (vgn) range 20 db/v, vref = 2.5 v 0.1 to 2.9 v input bias current ?0.4 m a input resistance 2m w response time 48 db gain change 0.2 m s vref input resistance 10 k w power supply specified operating range one complete channel 5v one dsx only 5 v power dissipation one complete channel 220 mw one dsx only 95 mw quiescent supply current vpos, one complete channel 32 36 ma vpos, one dsx only 19 23 ma vneg, one preamplifier only ?15 ?12 ma powered down vpos, vgn < 50 mv, one channel 1.9 3.0 ma vneg, vgn < 50 mv, one channel ?150 m a power-up response time 48 db gain change, v out = 2 v p-p 0.6 m s power-down response time 0.4 m s warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad604 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2, 3 supply voltage v s pins 17, 18, 19, 20 (with pins 16, 22 = 0 v) . . . . . . 6.5 v input voltages pins 1, 2, 11, 12 . . . . . . . . . . . . . vpos/2 2 v continuous pins 4, 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 v pins 5, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vpos, vneg pins 6, 7, 13, 14, 23, 24 . . . . . . . . . . . . . . . . . . . . . vpos, 0 internal power dissipation pdip (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 w soic (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 w ssop (rs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 w operating temperature range . . . . . . . . . . . ?40 c to +85 c storage temperature range . . . . . . . . . . . . ?65 c to +150 c lead temperature, soldering 60 sec . . . . . . . . . . . . . . . 300 c ja 4 ad604an . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 c ad604ar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 c ad604ars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 c jc 4 ad604an . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 c ad604ar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 c ad604ars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 c ordering guide temperature package model range option description ad604an ?40 c to +85 c n-24 pdip ad604ar ?40 c to +85 c r-24 soic ad604ar-reel ?40 c to +85 c r-24 soic ad604ars ?40 c to +85 c rs-24 ssop ad604ars-reel ?40 c to +85 c rs-24 ssop ad604ars-reel7 ?40 c to +85 c rs-24 ssop AD604-EB evaluation board notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 pins 1, 2, 11, 12, 13, 14, 23, 24 are part of a single-supply circuit. the part will most likely be damaged if any of these pins are accidentally connected to vn. 3 when driven from an external low impedance source. 4 using mil std 883 test method g43-87 with a 1s (2-layer) test board.
rev. a ? ad604 pin function descriptions pin no. mnemonic description 1 ?dsx1 ch1 negative signal input to dsx1. 2 +dsx1 ch1 positive signal input to dsx1. 3 pao1 ch1 preamplifier output. 4 fbk1 ch1 preamplifier feedback pin. 5 pai1 ch1 preamplifier positive input. 6 com1 ch1 signal ground. when connected to positive supply, preamplifier 1 will shut down. 7 com2 ch2 signal ground. when connected to positive supply, preamplifier 2 will shut down. 8 pai2 ch2 preamplifier positive input. 9 fbk2 ch2 preamplifier feedback pin. 10 pao2 ch2 preamplifier output. 11 +dsx2 ch2 positive signal input to dsx2. 12 ?dsx2 ch2 negative signal input to dsx2. 13 vgn2 ch2 gain-control input and power-down pin. if grounded, device is off; otherwise, positive voltage increases gain. 14 vocm input to this pin defines the common-mode of the output at out1 and out2. 15 out2 ch2 signal output. 16 gnd2 ground. 17 vpos positive supply. 18 vneg negative supply. 19 vneg negative supply. 20 vpos positive supply. 21 gnd1 ground. 22 out1 ch1 signal output. 23 vref input to this pin sets gain-scaling for both channels to 2.5 v = 20 db/v, 1.67 v = 30 db/v. 24 vgn1 ch1 gain-control input and power-down pin. if grounded, the device is off; otherwise, positive voltage increases gain. pin configuration ?dsx1 +d sx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 +d sx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ad604
rev. a t ypical performance characteristics?d604 ? unless otherwise noted, g (preamp) = 14 db, vref = 2.5 v (20 db/v scaling), f = 1 mhz, r l = 500 , c l = 5 pf, t a = 25 c, v ss = 5v vgn (v) 50 20 ?10 0.1 2.9 40 30 10 0 0.5 0.9 1.3 1.7 2.1 2.5 gain (db) 3 curves ?40 c, +25 c, +85 c figure 1. gain vs. vgn for three temperatures gain scaling (db/v) 40.0 37.5 32.5 30.0 25.0 20.0 22.5 27.5 35.0 1.25 1.50 1.75 2.00 2.25 2.50 theoretical actual vref (v) figure 4. gain scaling vs. vref vgn (v) gain error (db) 2.0 0.2 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0.7 1.2 1.7 2.2 2.7 30db/v vref = 1.67v 20db/v vref = 2.50v figure 7. gain error vs. vgn for different gain scalings vgn (v) 60 0.1 50 40 30 20 10 0 ?10 ?20 0.5 0.9 1.3 1.7 2.1 2.5 2.9 g (preamp) = +14db (0db ? +48db) g (preamp) = +20db (+6db ? +54db) dsx only ( ?14db ? +34db) gain (db) figure 2. gain vs. vgn for different preamp gains vgn (v) gain error (db) 2.0 0.2 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0.7 1.2 1.7 2.2 2.7 ?40 c +25 c +85 c figure 5. gain error vs. vgn at different temperatures delta gain (db) percentage 25 ?1.0 20 15 10 5 0 ?0.8 ?0.6 ?0.4 ?0.2 0.1 0.3 0.5 0.7 0.9 g(db) = g(ch1) ? g(ch2) vgn1 = 1.0v vgn2 = 1.0v n = 50 figure 8. gain match; vgn1 = vgn2 = 1.0 v vgn (v) 50 20 ?10 0.1 2.9 40 30 10 0 0.5 0.9 1.3 1.7 2.1 2.5 actual actual 30db/v vref = 1.67v v 20db/ vref = 2.50v gain (db) figure 3. gain vs. vgn for different gain scalings vgn (v) gain error (db) 2.0 0.2 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0.7 1.2 1.7 2.2 2.7 freq = 5mhz freq = 10mhz freq = 1mhz figure 6. gain error vs. vgn at different frequencies delta gain (db) percentage 25 ?1.0 20 15 10 5 0 ?0.8 ?0.6 ?0.4 ?0.2 0.1 0.3 0.5 0.7 0.9 g(db) = g(ch1) ? g(ch2) vgn1 = 2.50v vgn2 = 2.50v n = 50 figure 9. gain match: vgn1 = vgn2 = 2.50 v
rev. a ? ad604 frequency (hz) gain (db) 50 40 ?50 100k 1m 10m 100m 30 20 10 0 ?10 ?20 ?30 ?40 vgn = 1.5v vgn = 2.9v vgn = 2.5v vgn = 0.1v vgn = 0.5v vgn = 0.0v figure 10. ac response vgn (v) 1000 1 0.1 0.1 2.9 100 10 0.5 0.9 1.3 1.7 2.1 2.5 noise (nv/ hz ) figure 13. input referred noise vs. vgn 10 1 0.1 110 1 k 100 r source alone vgn = 2.9v r source ( ) noise (nv/ hz ) figure 16. input referred noise vs. r source vgn (v) 2.55 0.2 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.45 0.7 1.2 1.7 2.2 2.7 vocm = 2.50v v out (v) 2.46 2.47 ?40 c +25 c +85 c figure 11. output offset vs. vgn noise (pv/ hz 900 850 800 750 700 650 600 temperature ( c) ?40 ?20 20 40 60 80 vgn = 2.9v 0 90 figure 14. input referred noise vs. temperature r source db 16 11 1 10 k 100 1k 6 15 14 13 12 10 9 8 7 5 3 4 2 vgn = 2.9v 10 1 figure 17. noise figure vs. r source vgn (v) 210 0.1 190 170 150 130 110 90 0.5 0.9 1.3 1.7 2.1 2.5 2.9 noise (nv/ hz ) +85 c +25 c ?40 c figure 12. output referred noise vs. vgn frequency (hz) 770 745 740 760 765 750 755 100k 1m 10m vgn = 2.9v noise (pv/ hz ) figure 15. input referred noise vs. frequency vgn (v) db 40 20 0 0 1.2 35 30 25 15 10 5 0.4 0.8 1.6 2.0 2.4 2.8 r s = 240 figure 18. noise figure vs. vgn
rev. a ad604 ? frequency (hz) harmonic distortion (dbc) ?40 ?50 ?70 100k ?60 ?45 ?55 ?65 1m 10m 100m v o = 1v p-p vgn = 1.0v hd2 hd3 figure 19. harmonic distortion vs. frequency frequency (mhz) p out (dbm) ?90 ?120 9.96 9.98 10.00 10.02 10.04 ?30 ?80 ?100 ?110 ?60 ?70 ?40 ?50 v o = 1v p-p vgn = 1.0v ?20 figure 22. intermodulation distortion 100ns/div 400mv/div v o = 2v p-p vgn = 1.5v 2v ?2v 253ns 1.253 s figure 25. large signal pulse response vgn (v) harmonic distortion (dbc) ?30 ?60 ?80 0.5 2.1 2.9 ?40 ?50 ?70 0.9 1.3 1.7 2.5 hd2(1mhz) hd3(1mhz) v o = 1v p-p hd3(10mhz) hd2(10mhz) ?35 ?65 ?45 ?55 ?75 figure 20. harmonic distortion vs. vgn vgn (v) 5 ?15 ?35 0.1 1.3 0 ?5 ?10 ?20 ?30 ?25 0.5 0.9 1.7 2.1 10mhz 1mhz input signal limit 800mv p-p 2.5 2.9 p in (dbm) figure 23. 1 db compression vs. vgn 100ns/div 40mv/div v o = 200mv p-p vgn = 1.5v 200 ?200 253ns 1.253 s trig'd figure 26. small signal pulse response ?20 ?50 ?80 0 harmonic distortion (dbc) 200 250 ?30 ?40 ?70 ?60 50 150 100 hd3(10mhz) hd2(10mhz) hd3(1mhz) hd2(1mhz) r s dut 50 500 v o = 1v p-p vgn = 1.0v r source ( ) figure 21. harmonic distortion vs. r source vgn (v) ip3 (dbm) 25 20 ?15 0.4 0.9 2.9 1.4 1.9 2.4 5 0 ?5 ?10 15 10 v o = 1v p-p f = 1mhz f = 10mhz figure 24. third-order intercept vs. vgn 10 0% 100 90 500mv 200ns 500mv 2.9v 0v vgn (v) figure 27. power-up/down response
rev. a ? ad604 10 0% 100 90 500mv 100ns 500mv 2.9v 0.1v vgn (v) figure 28. gain response frequency (hz) 1m 1k 1 1k 1m 100m 100k 10k 100 10 10k 100k input impedance ( ) 10m figure 31. input impedance vs. frequency frequency (hz) 100k 1m 100m 10m vgn = 0.1v vgn = 2.9v 20 14 6 8 10 12 16 18 delay (ns) figure 34. group delay vs. frequency frequency (hz) crosstalk (db) ?30 ?10 ?20 ?40 ?50 ?60 0 ?70 100k 1m 100m 10m vgn2 = 2.9v vgn2 = 2.0v vgn2 = 1.5v vgn1 = 1v v out1 = 1v p-p v in2 = gnd vgn2 = 0.1v figure 29. crosstalk (ch1 to ch2) vs. frequency temperature ( c) input bias current ( a) 27.6 25.8 20 27.2 26.8 26.6 26.2 ?20 0 40 ?40 26.0 26.4 27.0 27.4 60 80 90 figure 32. input bias current vs. temperature frequency (hz) cmrr (db) ?50 ?10 ?20 ?30 ?40 ?60 0 100k 1m 100m 10m v gn = 2.9v vgn = 0.1v vgn = 2.0v vgn = 2.5v figure 30. dsx common-mode rejection vs. frequency temperature ( c) supply current (ma) 40 20 0 35 30 25 15 10 5 ?40 40 90 ?20 0 20 60 80 ad604 (+i s ) dsx (+i s ) pre-amp ( i s ) +i s (ad604) = +i s (pa) + +i s (dsx) ?i s (ad604) = ?i s (pa) +i s (vgn = 0) figure 33. supply current (one channel) vs. temperature
rev. a ad604 ? theory of operation the ad604 is a dual-channel, variable gain amplifier with an ultralow noise preamplifier. figure 35 shows the simplified block diagram of one channel. each channel consists of: (1) a preamplifier with gain setting resistors r5, r6, and r7 (2) a single-supply x-amp ? (hereafter called dsx, differential single-supply x-amp) made up of: (a) a precision passive attenuator (differential ladder) (b) a gain control block (c) a vocm buffer with supply-splitting resistors r3 and r4 (d) an active feedback amplifier 1 (afa) with gain-setting resistors r1 and r2 the preamplifier is powered by a 5 v supply, while the dsx uses a single +5 v supply. the linear-in-db gain response of the ad604 can generally be described by: g gain scaling / gain control preamp gain db db v v db db () = () () () () + () () () ? 19 (1) each channel provides between 0 db to 48.4 db through 6 db to 54.4 db of gain depending on the user determined preampli- fier gain. the center 40 db of gain is exactly linear-in-db while the gain error increases at the top and bottom of the range. the gain of the preamplifier is typically either 14 db or 20 db but can be set to intermediate values by a single external resistor (see preamplifier section for details). the gain of the dsx can vary from ?14 db to +34.4 db, as is determined by the gain con- trol voltage (vgn). the vref input establishes the gain scaling; the useful gain scaling range is between 20 db/v and 40 db/v f or a vref voltage of 2.5 v and 1.25 v, respectively. for example, if the preamp gain was set to 14 db and vref was set to 2.50 v (to establish a gain scaling of 20 db/v), the gain equation would simplify to g vgn db db v v db () = () () () () 20 5 /? the desired gain can then be achieved by setting the unipolar gain control (vgn) to a voltage within its nominal operating range of 0.25 v to 2.65 v (for 20 db/v gain scaling). the gain is monotonic for a complete gain control voltage range of 0.1 v to 2.9 v. maximum gain can be achieved at a vgn of 2.9 v. since the two channels are identical, only channel 1 will be used to describe their operation. vref and vocm are the only inputs that are shared by the two channels, and since they are normally ac grounds, crosstalk between the two channels is minimized. for highest gain scaling accuracy, vref should have an external low impedance voltage source. for low accu- racy 20 db/v applications, the vref input can be decoupled with a capacitor to ground. in this mode, the gain scaling is determined by the midpoint between +v cc and gnd, so care should be taken to control the supply voltage to 5 v. the input resistance looking into the vref pin is 10 k w 20%. the dsx portion of the ad604 is a single-supply circuit, and the vocm pin is used to establish the dc level of the midpoint of this portion of the circuit. vocm needs only an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 v, gnd); however, if the dc level of the output is important to the user (see the applications section for ad9050 example), then vocm can be specifically set. the input resistance looking into the vocm pin is 45 k w 20%. preamplifier the input capability of the following single-supply dsx (2.5 2v for a +5 v supply) limits the maximum input voltage of the preamplifier to 400 mv for the 14 db gain configuration or 200 mv for the 20 db gain configuration. the preamplifier?s gain can be programmed to 14 db or 20 db by either shorting the fbk1 node to pao1 (14 db) or by leaving node fbk1 open (20 db). these two gain settings are very accurate since they are set by the ratio of on-chip resistors. any intermediate gain can be achieved by connecting the appro- priate resistor value between pao1 and fbk1 according to equations 2 and 3. g= v v r7 r r5 r6 r6 out in ext = () ++ (2) r r6 g ? r5 r6 r7 r7 r6 g r5 r6 ext = + () [] () ++ () ? (3) fbk c1 v ref vgn pai pao +dsx ?dsx ext. com vpos vocm c3 c2 out differential attenuator distributed g m 175 g1 gain control ao g2 ext. 175 r2 20 r1 820 r7 40 r5 32 r6 8 r4 200k r3 200k figure 35. simplified block diagram of a single channel of the ad604 1 to understand the active-feedback amplifier topology, refer to the ad830 data sheet. the ad830 is a practical implementation of the idea.
rev. a ?0 ad604 since the internal resistors have an absolute tolerance of 20%, the gain can be in error by as much as 0.33 db when r ext is 30 w , where it was assumed that r ext is exact. figure 36 shows how the preamplifier is set to gains of 14, 17.5, and 20 db. the gain range of a single channel of the ad604 is 0 db to 48 db when the preamplifier is set to 14 db (f igure 36a), 3.5 db to 51.5 db for a preamp gain of 17.5 db (figure 36b), and 6 db to 54 db for the highest preamp gain of 20 db (figure 36c). fbk1 pao1 com1 pai1 r6 8 r5 32 r7 40 a. preamp gain = 14 db fbk1 pao1 com1 pai1 r6 8 r5 32 r7 40 r10 40 b. preamp gain = 17.5 db fbk1 pao1 com1 pai1 r6 8 r5 32 r7 40 c. preamp gain = 20 db figure 36. preamplifier gain programmability for a preamplifier gain of 14 db, the preamplifier?s ?3 db small signal bandwidth is 130 mhz; when the gain is at the high end (20 db), the bandwidth will be reduced by a factor of two to 65 mhz. figure 37 shows the ac responses for the three preamp gains discussed above; note that the gain for an r ext of 40 w should be 17.5 db, but the mismatch between the internal resis- tors and the external resistor has caused the actual gain for this particular preamplifier to be 17.7 db. the ?3 db small signal bandwidth of one complete channel of the ad604 (preamplifier and dsx) is 40 mhz and is independent of gain. 20 19 10 100k 1m gain (db) 10m 100m 18 17 16 15 14 13 12 11 open 40 short 50 40 r ext 150 8 32 in v in r ext ( ) figure 37. ac responses for preamplifier gains shown in figure 36. to achieve its optimum specifications, power and ground man- agement are critical to the ad604. large dynamic currents result because of the low resistances needed for the desired noise performance. most of the difficulty is with the very low gain setting resistors of the preamplifier that allow for a total input referred noise, including the dsx, as low as 0.8 nv/ hz . the consequently large dynamic currents have to be carefully handled to maintain performance even at large signal levels. to accommodate these large dynamic currents as well as a ground referenced input, the preamplifier is operated from a dual 5 v supply. this causes the preamplifier?s output to also be ground referenced, which requires a common-mode level shift into the single-supply dsx. the two external coupling capacitors (c1, c2 in figure 35) connected to nodes pao1 and +dsx, and ?dsx and ground, respectively, perform this func- tion (see the ac coupling section). in addition, they eliminate any offset that would otherwise be introduced by the preampli- fier. it should be noted that an offset of 1 mv at the input of the dsx will get amplified by 34.4 db ( 52.5) when the gain- control voltage is at its maximum; this equates to 52.5 mv at the output. ac coupling is consequently required to keep the offset from degrading the output signal range. the internal feedback resistors setting the gain of the preampli fier are so small (nominally 8 w and 32 w ) that even an additional 1 w in the ?ground? connection at pin com1, which serves as the input common-mode reference, will seriously degrade gain accuracy and noise performance. this node is very sensitive and careful attention is necessary to minim ize the ground impedance. all connections to node com1 should be as short as possible. the preamplifier including the gain setting resistors has a noise performance of 0.71 nv/ hz and 3 pa/ hz . note that a signifi- cant portion of the total input referred voltage noise is due to the feedback resistors. the equivalent noise resistance presented by r5 and r6 in parallel is nominally 6.4 w , which contributes 0.33 nv/ hz to the total input referred voltage noise. the larger portion of the input referred voltage noise is coming from the amplifier with 0.63 nv/ hz . the current noise is independent of gain and depends only on the bias current in the input stage of the preamplifier?it is 3 pa/ hz . the preamplifier can drive 40 w (the nominal feedback resis- tors) and the following 175 w ladder load of the dsx with low distortion. for example, at 10 mhz and 1 v at the output, the preamplifier has less than ?45 db of second and third harmonic distortion when driven from a low (25 w ) source resistance. in some cases, one may need more than 48 db of gain range, in which case two ad604 channels could be cascaded. since the preamplifier has limited input signal range, consumes over half (120 mw) of the total power (220 mw), and its ultralow noise is not necessary after the first ad604 channel, a shutdown mechanism that disables only the preamplifier is built in. all that is required to shut down the preamplifier is to tie the com1 and/or com2 pin to the positive supply. the dsx will be unaffected and can be used as before (see the applications section for further details).
rev. a ad604 ?1 12 11 10 9 8 1 2 3 4 7 6 5 13 16 15 14 24 23 22 21 20 19 18 17 ad604 ?dsx1 +d sx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 +d sx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 figure 38. shutdown of preamplifiers only differential ladder (attenuator) the attenuator before the fixed gain amplifier of the dsx is realized by a differential 7-stage r-1.5r resistive ladder network with an untrimmed input resistance of 175 w single-ended or 350 w differential. the signal applied at the input of the ladder network (figure 39) is attenuated by 6.908 db per tap; thus, the attenuation at the first tap is 0 db, at the second, 13.816 db, and so on, all the way to the last tap where the attenuation is 48.356 db. a unique circuit technique is used to interpolate continuously between the tap points, thereby provid- ing continuous attenuation from 0 to ?48.36 db. think of the ladder network together with the interpolation mechanism as a voltage-controlled potentiometer. since the dsx is a single-supply circuit, some means of biasing its inputs must be provided. node mid together with the vocm buffer perform this function. without internal biasing, the user would have had to dc bias the inputs externally. if not done carefully, the biasing network can introduce additional noise and offsets. by providing internal biasing, the user is relieved of this task and only needs to ac couple the signal into the dsx. it should be made clear again that the input to the dsx is still fully differential if driven differentially, i.e., pins +dsx and ?dsx see the same signal but with opposite polarity (see the ultralow noise, differential input-differential output vga section). what changes is the load as seen by the driver; it is 175 w when each input is driven single ended, but 350 w when driven differentially. this can be easily explained when thinking of the ladder network as just two 175 w resistors con- nected back-to-back with the middle node, mid, being biased by the vocm buffer. a differential signal applied between nodes +dsx and ?dsx results in zero current into node mid, but a single-ended signal applied to either input, +dsx or ?dsx while the other input is ac grounded causes the current delivered by the source to flow into the vocm buffer via node mid. the ladder resistor value of 175 w was chosen to provide the optimum balance between the load driving capability of the preamplifier and the noise contribution of the resistors. one feature of the x-amp architecture is that the output referred noise is constant versus gain over most of the gain range. this can be easily explained by looking at figure 39 and observing that the tap resistance is equal for all taps after only a few taps away from the inputs. the resistance seen looking into each tap is 54.4 w , which makes 0.95 nv/ hz of johnson noise spectral density. since there are two attenuators, the overall noise contri- bution of the ladder network is 2 times 0.95 nv/ hz or 1.34 nv/ hz , a large fraction of the total dsx noise. the rest of the dsx circuit components contribute another 1.20 nv/ hz, which together with the attenuator produces 1.8 nv/ hz of total dsx input referred noise. ac coupling as already mentioned, the dsx portion of the ad604 is a single- supply circuit and therefore its inputs need to be ac- coupled to accommodate ground based signals. external capacitors c1 and c2 in figure 35 level shift the ground referenced preampli fier output from ground to the dc value established by vocm (nominal 2.5 v). c1 and c2, together with the 175 w looking into each of the dsx inputs (+dsx and ?dsx), act as high- pass filters with corner frequencies depending on the values chosen for c1 and c2. for example, if c1 and c2 are 0.1 m f, then together with the 175 w input resistance seen into each side of the differential ladder of the dsx, a ?3 db high-pass corner at 9.1 khz is formed. if the ad604 output needs to be ground referenced, another ac coupling capacitor is required for level shifting. this capacitor also eliminates any dc offsets contributed by the dsx. with a nominal load of 500 w and a 0.1 m f coupling capacitor, this adds a high-pass filter with ?3 db corner frequency at about 3.2 kh z. the choice for all three of these coupling capacitors depends on the application. they should allow the signals of interest to pass unattenuated, while at the same time they can be used to limit the low frequency noise in the system. r ?6.908db r 1.5r 1.5r r r ?13.82db r 1.5r 1.5r r ?20.72db r 1.5r 1.5r r ?27.63db r 1.5r 1.5r r ?34.54db r 1.5r 1.5r r ?41.45db r 1.5r 1.5r r ?48.36db 1.5r 1.5r 175 175 + dsx mid ?dsx note: r = 96 1.5r = 144 figure 39. r?.5r dual ladder network.
rev. a ?2 ad604 gain control interface the gain-control interface provides an input resistance of ap proximately 2 m w at pin vgn1 and gain scaling factors from 20 db/v to 40 db/v for vref input voltages of 2.5 v to 1.25 v respectively. the gain scales linearly-in-db for the center 40 db of gain range, that is for vgn equal to 0.4 v to 2.4 v for the 20 db/v scale and 0.2 v to 1.2 v for the 40 db/v scale. figure 40 shows the ideal gain curves for a nominal preamplifier gain of 14 db, which are described by the following equations: g / vgn ? , vref 20 20 5 2 500 db v v () = = . (4) g / vgn ? , vref 20 30 5 1 666 db v v () = = . (5) g / vgn ? , vref 20 40 5 1 250 db v v () = = . (6) gain control voltage (vgn) 20 40 35 30 25 15 10 5 50 45 0 ?5 linear-in-db range of ad604 with preamplifier set to 14db 0.5 1.0 2.5 1.5 2.0 3.0 gain (db) 30db/v 40db/v 20db/v figure 40. ideal gain curves vs. vref from these equations, it can be seen that all gain curves inter- cept at the same ?5 db point; this intercept will be +6 db higher (+1 db) if the preamplifier gain is set to +20 db or +14 db, lower (?19 db) if the preamplifier is not used at all. outside of the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 db of range. for a given gain scaling, vref can be calculated as shown in equation 7: vref gain scale = 2 500 20 ./ vdbv (7) usable gain control voltage ranges are 0.1 v to 2.9 v for 20 db/v scale and 0.1 v to 1.45 v for the 40 db/v scale. vgn voltages of less than 0.1 v are not used for gain control since below 50 mv the channel (preamp and dsx) is powered down. this can be used to conserve power and at the same time gate off the signal. the supply current for a powered-down channel is 1.9 ma; the response time to power the device on or off is less than 1 m s. active feedback amplifier (fixed gain amp) to achieve single-supply operation and a fully differential input to the dsx, an active-feedback amplifier (afa) is utilized. the afa is basically an op amp with two g m stages; one of the active stages is used in the feedback path (therefore the name), while the other is used as a differential input. note that the differen- tial input is an open-loop g m stage that requires it to be highly linear over the expected input signal range. in this design, the g m stage that senses the voltages on the attenuator is a distrib- uted one; for example, there are as many g m stages as there are taps on the ladder network. only a few of them are on at any one time, depending on the gain-control voltage. the afa makes a differential input structure possible since one of its inputs (g1) is fully differential; this input is made up of a distributed g m stage. the second input (g2) is used for feed- back. the output of g1 will be some function of the voltages sensed on the attenuator taps which is applied to a high gain amplifier (a0). because of negative feedback, the differential input to the high gain amplifier has to be zero; this in turn implies that the differential input voltage to g2 times g m2 (the transconductance of g2) has to be equal to the differential input voltage to g1 times g m1 (the transconductance of g1). therefore, the overall gain function of the afa is v v g g r1 r2 r2 out atten m1 m2 = + (8) where v out is the output voltage, v atten is the effective voltage sensed on the attenuator, ( r1 + r2 )/ r2 = 42, and g m1 / g m2 = 1.25; the overall gain is thus 52.5 (34.4 db). the afa has additional features: (1) inverting the signal by switching the positive and negative input to the ladder network, (2) the possibility of using the dsx1 input as a second signal input, (3) fully differential high impedance inputs when both preamplifiers are used with one dsx (the other dsx could still be used alone), and (4) independent control of the dsx com- mon-mode voltage. under normal operating conditions, it is best to connect a decoupling capacitor to pin vocm in which case the common-mode voltage of the dsx is half the supply voltage; this allows for maximum signal swing. nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to vocm. it can also be used as another signal input, the only limitation being the rather low slew rate of the vocm buffer. if the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the dsx; again this is done for level shifting and to eliminate any dc off- sets contributed by the dsx (see the ac coupling section).
rev. a ad604 ?3 applications the most basic circuit in figure 41 shows the connections for one channel of the ad604. the signal is applied at pin 5. rgn is normally 0, in which case the preamplifier is set to a gain of 5 (14 db). when pin fbk1 is left open, the pream plifier is set to a gain of 10 (20 db) and the gain range shifts up by 6 db. the ac coupling capacitors before pins ?dsx1 and +dsx1 should be selected according to the required lower cutoff frequency. in this example, the 0.1 m f capacitors together with the 175 w seen looking into each of the dsx input pins provide a ?3 db high-pass corner of about 9.1 khz. the upper cutoff frequency is deter- mined by the bandwidth of the channel, which is 40 mhz. note that the signal can be simply inverted by connecting the output of the preamplifier to pin ?dsx1 instead of +dsx1; this is due to the fully differential input of the dsx. 12 11 10 9 8 1 2 3 4 7 6 5 13 16 15 14 24 23 22 21 20 19 18 17 ad604 v in vgn rgn 2.500v +5v ?5v out ?dsx1 +d sx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 +d sx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 0.1 f r l 500 0.1 f 0.1 f 0.1 f figure 41. basic connections for a single channel as shown here, the output is ac coupled for optimum perfor- mance. in the case of connecting to the ad9050, ac coupling can be eliminated as long as pin vocm is biased by the same 3.3 v common-mode voltage as the ad9050 (see figure 50). pin vref requires a voltage of 1.25 v to 2.5 v, with between 40 db/v and 20 db/v gain scaling, respectively. voltage vgn controls the gain; its nominal operating range is from 0.25 v to 2.65 v for 20 db/v gain scaling and 0.125 v to 1.325 v for 40 db/v scaling. when this pin is taken to ground, the channel will power down and disable its output. pin com1 is the main signal ground for the preamplifier and needs to be connected with as short a connection as possible to the input ground. since the internal feedback resistors of the preamplifier are very small for noise reasons (8 w and 32 w nominally), it is of utmost importance to keep the resistance in this connection to a minimum. furthermore, excessive induc- tance in this connection may lead to oscillations. as a consequence of the ad604?s ultralow noise and wide band- width, large dynamic currents flow to and from the power su pply. to ensure the stability of the part, extreme attention to supply decoupling is required. a large storage capacitor in parallel with a smaller high frequency capacitor connected right at the supply pins, together with a ferrite bead coming from the supply should be used to ensure high frequency stability. to provide for additional flexibility, pin com1 can be used to depower the preamplifier. when com1 is connected to vp, the preamplifier is off, yet the dsx portion can be used inde- pendently. this may be of value when one desires to cascade the two dsx stages in the ad604. in this case, the first dsx output signal with respect to noise is large and using the second preamplifier at this point would waste power (see agc ampli- fier application). an ultralow noise agc amplifier with 82 db to 96 db gain range figure 42 shows an implementation of an agc amplifier with 82 db of gain range using a single ad604. first, the connec- tions for the two channels of the ad604 are discussed; second, how the detector circuitry that closes the loop works is discussed. vg 13 16 15 14 19 18 17 24 23 22 21 20 12 11 10 9 8 1 2 3 4 7 6 5 ad604 ?5v +5v vref r2 453 rf out ?5v +5v 8 7 6 5 1 2 3 4 ad711 ?v s nc +v s out 8 765 1234 y1 y2 vn z x1 x2 vp w ad835 +5v ?5v ?5v +5v ? (a) 2 2 if v1 = a cos (wt) vset (<0v) ?dsx1 +d sx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 +dsx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 fb fb +5v ?5v all supply pins are decoupled as shown. r1 49.9 vin (max 800mv p-p) c2 0.1 f c1 0.1 f c3 0.1 f c4 0.1 f c12 0.1 f c13 0.1 f c7 0.1 f c6 0.56 f c7 0.33 f r3 1k v1 = v in g c8 0.33 f r4 2k c9 0.33 f r5 2k r6 2k ? (v1) 2 1v low- pass filter r7 1k c10 1 f r8 2k c11 1 f offs null offs null figure 42. agc amplifier with 82 db of gain range
rev. a ?4 ad604 the signal is applied to connector vin, and since the signal source was 50 w , a terminating resistor (r1) of 50 w was added. the signal is then amplified by 14 db (pin fbk1 shorted to pao1) through the channel 1 preamplifier and is further processed by the channel 1 dsx. next the signal is applied directly to the channel 2 dsx. the second preamplifier is powered down by connecting its com2 pin to the positive supply as explained in the preamplifier section. capacitors c1 and c2 level shift the signal from the preamplifier into the first dsx and at the same time eliminate any offset contribution of the preamp. c3 and c4 have the same offset cancellation pur pose for the second dsx. each set of capacitors together with the 175 w input resistance of the corresponding dsx provides a high-pass filter with ? db corner frequency of about 9.1 khz. pin vocm is decoupled to ground by a 0.1 m f capacitor, while vref can be externally provided; in this application, the gain scale is set to 20 db/v by applying 2.500 v. since each of the dsx amplifiers operates from a single 5 v supply, the output is ac coupled via c6 and c7. the output signal can be monitored at the connector labeled rf out. figures 43 and 44 show the gain range and gain error for the ad604 connected as shown. the gain range is ?4 db to +82 db; the useful range is 0 db to +82 db if the rf output amplitude is controlled to 400 mv (+2 dbm). the main limitation on the lower end of the signal range is the input capability of the preamplifier. this can be overcome by adding an attenuator in front of the preamplifier, but that would defeat the advantage of the ultralow noise preamplifier. it should be noted that the second preamplifier is not used since its ultralow noise and the associated high power consumption are overkill after the first dsx stage. it is disabled in this application by connecting the com2 pin to the positive supply. nevertheless, the second preamplifier can be used if so desired, and the useful gain range will shift up by 14 db to encompass 0 db to 96 db of gain. for the same +2 dbm output, this allows signals as small as ?4 dbm to be measured. to achieve the highest gains, the input signal has to ultimately be bandlimited to reduce the noise; this is especially true if the second preamplifier is used. if the maxim um signal at pin out2 of the ad604 is limited to 400 mv (+2 dbm), the input signal level at the agc threshold is +25 m v rms (79 dbm). the circuit as shown has about 40 mhz of noise bandwidth; the 0.8 nv/ hz of input referred voltage noise spectral density of the ad604 results in an rms noise of 5.05 m v in the 40 mhz bandwidth. the 50 w termination resistor, together with the 50 w source resistance of the signal generator, combine to an effective resis- tance as seen by the input of the preamplifier of 25 w , which makes 4.07 m v of rms noise in 40 mhz. the noise floor of this channel is consequently the rms sum of these two main noise sources, 6.5 m v rms. this means that the minimum detectable signal (mds) for this circuit is +6.5 m v rms (?0.7 dbm). as a general rule, the measured signal should be about a factor-of- three larger than the noise floor, in this case 19.5 m v rms. as we can see, the 25 m v rms signal that t his agc circuit can correct for is just slightly above the mds. of course, the sensitivity of the input can be improved by bandlimiting the signal; if the noise bandwidth is reduced by a factor-of-four to 10 mhz, the noise floor of the agc circuit with a 50 w termination resistor will drop to +3.25 m v rms (?6.7 dbm). further noise improvement can be achieved by an input matching network or by transformer coupling of the input signal. vgn (v) 90 80 ?30 70 60 20 50 40 30 ?20 ?10 0 10 1.7 0.1 0.5 0.9 1.3 2.1 2.5 2.9 gain (db) f = 1mhz figure 43. ad604 cascaded gain vs. vgn vgn (v) 4 3 ?4 2.2 2 1 ?3 0 ?1 ?2 0.2 0.7 1.2 1.7 2.7 gain error (db) f = 1mhz figure 44. ad604 cascaded gain error vs. vgn the descriptions of the detector circuitry functions, comprised of a squarer, a low-pass filter, and an integrator, will follow. at this point, it is necessary to make some assumptions about the input signal. the following explanation of the detector circuitry presumes an amplitude modulated rf carrier where the modu- lating signal is at a much lower frequency than the rf signal. the ad835 multiplier functions as the detector by squaring the output signal presented to it by the ad604. a low-pass filter following the squaring operation removes the rf signal compo- nent at twice the incoming signal frequency, while passing the low frequency am information. the following integrator with a time constant of 2 ms set by r8 and c11 integrates the error signal presented by the low-pass filter and changes vg until the error signal is equal to v set . for example, if the signal presented to the detector is v1 = a cos(wt) as indicated in figure 42, the output of the squarer is ?v1) 2 /1 v. the reason for all the minus signs in the detection circuitry comes from the necessity of providing negative feed- back in the control loop; actually if v set becomes greater than 0 v, the control loop provides positive feedback. squaring a cos(wt) results in two terms, one at dc and one at 2w; the following low-pass filter passes only the ?a) 2 /2 dc term. this dc voltage is now forced equal to the voltage, v set , by the con trol loop. the squarer, together with the low-pass filter, functions as a mean-square detector. as should be evident by control- ling the value of v set , we can set the amplitude of the voltage v1 at the input of the ad835; if v set equals ?0 mv, the agc output signal amplitude will be 400 mv.
rev. a ad604 ?5 figure 45 shows the control voltage, vgn, versus the input power at frequencies of 1 mhz (solid line) and 10 mhz (dashed line) at an output regulated level of 2 dbm (800 mv p-p). the agc threshold is evident at a p in of about ?79 dbm; the highest input power that could still be accommodated was about +3 dbm. at this level, the output starts being distorted because of clip- ping in the preamplifier. 4.5 4.0 0.5 0 ?40 3.5 3.0 1.0 2.5 2.0 1.5 ?80 ?70 ?60 ?50 ?30 ?20 ?10 1 0 control voltage (v) 1mhz 10mhz p in (dbm) figure 45. control voltage vs. input power of circuit in figure 42 as mentioned already, the second preamplifier can be used to extend the range of the agc circuit in figure 42. figure 46 shows the modifications that need to be made to figure 44 to achieve 96 db of gain and dynamic range. because of the ex tremely high gain, the bandwidth needs to be limited to reject some of the noise; furthermore, limiting the bandwidth will help suppress high frequency oscillations. the added components act as a low-pass filter and dc block (c5 level shifts the output of the first dsx from 2.5 v to ground); the ferrite bead has an impedance of about 5 w at 1 mhz, 30 w at 10 mhz, and 70 w at 100 mhz. together with r2 and c6, the bead makes a low- pass filter that attenuates higher frequencies; at 1 mhz the attenuation is about ?0.2 db, while at 10 mhz it increases to ?6 db, on to ?28 db at 100 mhz. signals now have to be less than about 1 mhz to not be significantly affected by the added circuitry. figure 47 shows the control voltage versus the input power at 1 mhz to the circuit in figure 46; note that the agc threshold is at ?95 dbm. the output signal level was set to 800 mv p-p by applying ?80 mv to the v set connector. 12 11 10 9 8 1 2 3 4 7 6 5 13 16 15 14 24 23 22 21 20 19 18 17 ad604 c6 560pf fb fair-rite #2643000301 ?dsx1 +d sx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 +d sx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 r2 499 c5 0.1 f c3 0.1 f figure 46. modifications of agc amplifier to create 96 db of gain range 4.5 4.0 0 ?100 0 ?40 3.5 3.0 1.0 2.5 2.0 1.5 ?90 ?80 ?70 ?60 ?50 ?30 ?20 ?10 10 control voltage (v) 1mhz 0.5 p in (dbm) figure 47. control voltage vs. input power of circuit in figure 46
rev. a ?6 ad604 ultralow noise, differential input-differential output vga figure 48 shows how to use both preamplifiers and dsxs to create a high impedance, differential input-differential output variable gain amplifier. this application takes advantage of the differential inputs to the dsxs. it should be pointed out that the input is not truly differential, in the sense that the common- mode voltage needs to be at ground to achieve maximum input signal swing. this has mainly to do with the limited output swing capability of the output drivers of the preamplifiers; they clip around 2.2 v due to having to drive an effective load of about 30 w . if a different input common-mode voltage needs to be accommodated, ac coupling (as was done in figure 46) is recommended. the differential gain range of this circuit runs from 6 db to 54 db. this is 6 db higher than each individual channel of the ad604 because the dsx inputs now see twice the signal amplitude compared to when they are driven single ended. 13 16 15 14 19 18 17 24 23 22 21 20 12 11 10 9 8 1 2 3 4 7 6 5 ad604 fb fb +5v ?5v all supply pins are decoupled as shown. +5v ?5v ?5v +5v vin+ vin? vg vref vout+ vout? ?dsx1 + dsx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 + dsx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 c13 0.1 f c12 0.1 f c3 0.1 f c4 0.1 f c1 0.1 f c2 0.1 f c5 0.1 f r2 453 c6 0.1 f c7 0.1 f r1 453 figure 48. ultralow noise, differential input differential output vga figure 49 displays the output signals vout+ and vout? after a ?20 db attenuator formed between the 453 w resistors shown in figure 48 and the 50 w loads presented by the oscilloscope plug-in. r1 and r2 were inserted to ensure a nominal load of 500 w at each output. the differential gain of the circuit was set to 20 db by applying a control voltage, vgn, of 1 v; the gain scaling was 20 db/v for a vref of 2.500 v; the input frequency was 10 mhz and the differential input amplitude 100 mv p-p. the resulting differential output amplitude was 1 v p-p as can be seen on the scope photo when reading the vertical scale as 200 mv/div. 10 0% 100 90 20ns 20mv 20mv + 500mv ?500mv actual v out note that the output after 10 attenuater formed by 453 together with 50 of 7a24 plug-in. figure 49. output of vga in figure 48 for v g = 1 v medical ultrasound tgc driving the ad9050, a 10-bit, 40 msps adc th e ad 604 is an ideal candidate for the time gain control (tgc) amplifier that is required in medical ultrasound systems to limit the dynamic range of the signal that is presented to the adc. figure 50 shows a schematic of an ad604 driving an ad9050 in a typical medical ultrasound application. the gain is controlled by means of a digital byte that is input to an ad7226 dac that outputs the analog gain control signal. the output common-mode voltage of the ad604 is set to vpos/2 by means of an internal voltage divider. the vocm pin is bypassed with a 0.1 m f capacitor to ground. the dsx output is optionally filtered and then buffered by an ad9631 op amp, a low distortion, low noise amplifier. the op amp output is ac-coupled into the self-biasing input of an ad9050 adc that is capable of outputting 10 bits at a 40 msps sampling rate.
rev. a ad604 ?7 13 16 15 14 19 18 17 24 23 22 21 20 12 11 10 9 8 1 2 3 4 7 6 5 ad604 +5v ?5v in1 vref out1 vocm vg1 vg2 out2 r3 rgn r2 rgn note 2 note 3 note 3 in2 pao2 pao1 notes: 1. pao1 and pao2 are used to measure preamps. 2. rgn = 0 nominally; preamp gain = 5, rgn = open; preamp gain = 10 3. when measuring bw with 50 spectrum analyzer, use 450 in series. ?dsx1 +d sx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 +d sx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 optional c3 0.1 f c1 0.1 f c6 0.1 f c5 0.1 f c7 0.1 f c9 0.1 f c10 0.1 f c8 5pf r4 500 c11 0.1 f c12 0.1 f c2 5pf r1 500 c4 0.1 f 0.1 f figure 51. basic test board 20 27 28 15 16 17 18 19 24 25 26 22 14 13 10 3 4 9 6 5 ad9050 comp vref in vref out ref bp ainb encode or ain ( msb) d9 d8 d5 d6 d7 d4 d3 d2 d1 ( lsb) d0 v dd a/d output 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 ad604 1k clk j2 analog input 12 11 20 19 18 17 16 15 14 13 10 9 8 1 2 3 4 7 6 5 ad7226 v out b v out a agnd v ref v ss dgnd db7 ( msb) db6 db5 db4 a1 a0 v dd wr db0 ( lsb) db1 db2 db3 vref +15v digital gain control filter 2 3 6 ad9631 optional ?in +in out ?dsx1 +d sx1 pai1 fbk1 pao1 com1 com2 pai2 fbk2 pao2 +d sx2 ?dsx2 vgn1 vref vpos gnd1 out1 vneg vneg vpos gnd2 out2 vocm vgn2 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 50 50 100 1k 1k 0.1 f 0.1 f 0.1 f 0.1 f v out c v out d v dd figure 50. tgc circuit for medical ultrasound application ad604 dut pai out r a hp3577b 0.1 f 450 50 49.9 hp11636b power splitter figure 52. setup for gain measurements
rev. a ?8 ad604 outline dimensions 24-lead standard small outline package [soic] wide body (r-24) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ad 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 24 13 12 1 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 15.60 (0.6142) 15.20 (0.5984) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) 24-lead plastic dual in-line package [pdip] (n-24) dimensions shown in inches and (millimeters) 24 1 12 13 1.185 (30.01) 1.165 (29.59) 1.145 (29.08) 0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) seating plane 0.015 (0.38) min 0.180 (4.57) max 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.100 (2.54) bsc 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-095ag
rev. a ad604 ?9 24-lead shrink small outline package [ssop] (rs-24) dimensions shown in millimeters 24 13 12 1 8.20 7.80 7.40 5.60 5.30 5.00 0.38 0.22 seating plane 0.05 min 0.65 bsc 2.00 max 1.85 1.75 1.65 0.95 0.75 0.55 0.25 0.09 8 4 0 0.10 coplanarity 8.50 8.20 7.90 compliant to jedec standards mo-150ag
rev. a c00540??/04(a) ?0 ad604 revision history location page 1/04?ata sheet changed from rev. 0 to rev. a. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to figure 1 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to figure 11 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to figure 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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